Abstract— Genetic algorithm (GA) is a design technique that synthesizes an application specific Network-on-chip (NoC) topology and routes the communication traces on the interconnection network. Network-on-chip (NoC) is a new paradigm for designing scalable communication architecture for SoC (system on chip). In this paper Genetic algorithm (GA) is proposed as a reliable and efficient technique for large NoC. It is based on automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. Initially NoC routers are implemented based on GA (genetic algorithm) optimization algorithm. Critical path analysis is performed initially in router architecture inorder to determine shortest path. As a result effective shortest path with less number of nodes is identified. Then fault analysis process is carried out in the obtained shortest path. As a result, a net fault free routing path is obtained. Genetic algorithm provides optimum mapping in NoC architecture and measures faulty blocks during run time more effectively. Experimental results show that test sets generated using the evolutionary approach are more compact and very effective than those generated by earlier approaches for many circuits. The design technique solves a multi-objective problem of reduction in power, area, latency and delay.
Index Terms— Genetic Algorithm, Network-On-Chip, critical and fault analysis.