Abstract — A FPGA Implementation of a bilateral filter for image processing is given which does spatial averaging without smoothing edges. Kernel based processing is possible, which means that processing of the entire filter window at one pixel clock cycle. It is also supported by the arrangement of the input data into groups and applied a single clock cycle for a group of pixels. Based on these features, a technique called Error Tolerant Adder (ETA) is implemented in Bilateral Filter to minimize Power Delay Product (PDP). ETA provides high accuracy and achieves both power consumption and average case performance.Furthermore, ETA to eliminate the carry propagation path and improve the speed.The ETA can be expanded to a proposed addition arithmetic in which the conventional adder is divided into two parts. In Bilateral Filter a kernel of different size can be implemented using ETA whichachieves good performance.
Index Terms — Bilateral filter, ETA, Image processing, noise reduction, PDP.