Abstract— an efficient architecture for the implementation of a delayed least mean square adaptive filter. A Novel partial product Generator is achieving lower adaptation-delay and Area delay consumption and propose a strategy for optimized balanced pipelining across the time-consuming combinational blocks of the structure. From synthesis results, the proposed design will offers less area-delay product (ADP) the best of the existing systolic structures, on average, for filter lengths N =8, 16, and 32. An efficient fixed-point implementation scheme of the proposed architecture, the analytical result matches with the simulation result is showed.
Index Terms—Adaptive filters, circuit optimization, fixed-point arithmetic, least mean square (LMS) algorithms.